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First use of the Zynq-7000 Processor System on a Zynq Board

Posted by Florent - 02 December 2016

Introduction

In this tutorial, we will use the Processor System (PS) part of a Zynq-7000 of a Zynq Board using the Vivado 2016.2. For this tutorial we will use a Xilinx ZC702 board but this could also been done on another board with a Xilinx Zynq -7000 SoC.

Configure the Processor System (PS) in Vivado

In this part, we will use Vivado to configure the Processor System part of the Zynq-7000. In particular we will see the mapping of the I/O peripherals (IOP) to the pins of the device.

Create a Vivado Project

Create a new Vivado RTL project targeting a ZC702 board. Create a new Block Diagram (BD) by clicking on “Create Block Diagram” in the flow navigator.

Figure 1 - Create a new Block Diagram in Vivado

Name the block diagram “zynq_platform”, keep the default settings for “Directory” and “Specify Source set” and click OK.

Figure 2 - Create Block Design

Add the Zynq SoC’s processing system in the BD by clicking at the add IP button and selecting ZYNQ7 Processing System. This IP is called a hard IP. It is already present in the Zynq SoC. Adding it to our project allow us only to select which component we want to enable an which pins we want to use (among the pins reserved for the PS).

Figure 3 – Add  ZYNQ7 Processing System IP

Configure the Zynq7 PS

Double click on the IP to configure it. There are default settings for the ZC702. Click on “Presets > ZC702”.

Figure 4 - ZC702 Presets

By doing this, Vivado configure the MIO (Multi-use IO) to map the IO peripherals that can be used with the ZC702 to the correct pins.

Figure 5 - XC7Z020 AP SoC to CP2103 Connections (source: Xilinx UG850)

For example, as mentioned in the Xilinx UG850, the ZC702 board contains a Silicon Labs CP2103GM USB-to-UART bridge device which allows a connection to a host computer with a USB port. The CP2013GM TX and RX pins are physically wired to the UART_1 IP block within the XC7Z020 AP SoC PS I/O Peripherals set. As shown in the Figure 5, the CP2013GM TX and RX pins are connected to the MIO48 and MIO49 pins of the FPGA.

If we click on “MIO configuration” in the Zynq7 PS customizing GUI, under “I/O peripherals” we can see that Vivado has correctly mapped the UART 1 to the MIO48 and MIO49. You can check/configure the UART Baud Rate in “PS-PL configuration” under “General”. By default, this should be 115200.                                                                                                                                               

Figure 6 - Zynq PS MIO Configuration

Exit the Zynq7 PS customizing GUI by clicking OK. In the BD, connect the output pin FCLK_CLK0 of the Zynq7 PS to its input pin M_AXI_GP0_ACLK.

Figure 7 - Connect the output pin FCLK_CLK0 of the Zynq7 PS to its input pin M_AXI_GP0_ACLK

Verify that the design is correct by clicking on the “Validate Design” icon. You should have no issue. Save the BD.

Generate the HDL files

In the source window, right click on the BD and click on “Generate Output Products”. This will generate the HDL files corresponding to the Zynq7 PS IP.

Figure 8 - Generate Output Products

In the “Generate Output Products” window, select “Global” and click on “Generate”. When the Output Products generation is over, right click again on the BD and click on “Create HDL Wrapper”.  On the “Create HDL Wrapper” window select “Let Vivado manage wrapper and auto-update”.

Figure 9 - Let Vivado manage wrapper and auto-update

You can see that a HDL (VHDL or Verilog) file has been created on the top of your BD. The file type (VHDL or Verilog) depends on your project settings. You can change it by clicking on “Project Setting” in the Flow Navigator and changing the setting for “Target language”.

Figure 10 - Target language setting

When the wrapper is created, click on “Generate Bitstream” in the Flow Navigator and click yes if a “No Implementation Results Available” window appears.

Program the PS using Xilinx SDK

Export the hardware to Xilinx SDK

To program the Zynq PS we will use the Xilinx tool SDK. First we need to export our PS configuration (and the generated Bitstream (optional)) to Xilinx SDK: In Vivado, click on “File > Export > Export Hardware”. In the “Export Hardware” window, select “Include Bitstream”.

Figure 11 - Export Hardware

When you leave the “Export to” option to “<Local to Project>”, the Hardware is exported in the folder “<project_folder>/<project_name>.sdk”. In this folder, the file exported is the file “zynq_platform_wrapper.hdf”, HDF standing for Hardware Definition File. An interesting thing to note is that this file is a compressed folder. If you open it using a tool such as 7-zip you can see that it contains several files including the Bitstream file “zynq_platform_wrapper.bit”.

Figure 12 - zynq_platform_wrapper.hdf file

Then, in Vivado, launch Xilinx SDK by clicking on “File > Launch SDK”. Keep the default settings in the “Launch SDK” window and click OK.

Test the Processing System with the “Hello World” project

In this part we will realize a bare-metal application. Bare-metal refers to a software system without an operating system.

In SDK, in the “Project Explorer” we can see the Hardware Platform “zynq_platform_wrapper_ hw_platform_0” created from our .hdf file (we can see that it includes the same files).

At least three parts are needed to have an application running on the Zynq PS:

· An hardware platform

· A bare-metal Board support Package (BSP). This is a collection of libraries and drivers that form the lowest layer of your application.

· Your application.

Create the application

To create a new “Hello World” application, click on “File > New > Application Project”. Name the application “hello_world”. Make sure that the “OS Platform value” is “standalone” which corresponds to a bare-metal application. You should have your hardware platform selected. We will use the first core (ps7_cortexa9_0). As you can see at the bottom of the window, Xilinx SDK will automatically create a BSP for our application containing all the drivers we will need.

Figure 13 - Create a new application in SDK

Click “NEXT”, select the “Hello World” template and click “FINISH”.

Figure 14 - Hello World template

Launch the application on the board

Build the application by clicking on the build icon. To test the application on the board, first make sure the the USB-to-JTAG and the USB-to-UART cables are connected from the PC to the board. Then power on the board. Program the FPGA by clicking on the program icon  and clicking on “Program”.

To launch the debbuger, select your application, click on the little arrow next to the debug icon and click on “Debug Configurations…

Figure 15 - Xilinx SDK - Debug Configurations

Right click on “Xilinx C/C++ application (GDB)” and click “New”.

Figure 16 - New Xilinx C/C++ Debug application (GDB)

When the new Xilinx C/C++ Debug application (GDB) has been create, click on “Debug”.

Figure 17 - Launch the Debug

If a new Debug window appears to ask you if you want to change for the Debug view, click YES.

Open an UART terminal to see the output of the console. You can open an “external” tool such as “Tera Term” or open an UART console in SDK by clicking on “Window > Show View > Other…” and selecting “Terminal”.

Figure 18 - Open an UART terminal in Xilinx SDK

In the terminal, click on the settings icon  to configure the terminal. Select “Serial” and “115200” as “Baud Rate”.

Figure 19 – UART terminal configuration

Launch the application by clicking on the Resume icon.

We can see “Hello World” printed in the console, showing that our application is correctly working.

Figure 20 - Hello World printed in the UART terminal

Understand the Software code

Figure 21 - Content of the file helloworld.c created by Xilinx SDK

The code of the application is shown in the Figure 21. You can see it by opening the file helloworld.c in the application hello_world.

Figure 22 - file helloworld.c created by Xilinx SDK

In the library declaration part of the file, we can see that 3 libraries are declared:

· stdio.h which is part of the standard C library.

· platform.h which contains the function prototypes init_platform() and cleanup_platform().

· xil_printf.h which contains Xilinx function for input/output data through the UART.

In the first line of the main(), the SW call the function init_platform() which initialize the platform. Basically, for our application this function will configure the UART. In the second line the function print() is called to send “Hello World” to the UART. This function is a simplified version of the printf() function from the stdio C standard library. The third line of the main() call the function cleanup_platform() which clean up the platform (disable cache). The last lane, “return 0” ends the program.



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