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First use of the Zynq-7000 Programmable Logic on a Zynq Board
In this tutorial, we will configure (i.e. program) the Programmable Logic (PL) part of a Zynq-7000 of a Zynq Board. For this tutorial we will use a Xilinx ZC702 board but this could also been done on another board with a Xilinx 7series FPGA. The equivalences to try it on a ZedBoard or on a ZYBO are given (but not checked).
Control LEDs from the switches
In this part we will create a Vivado RTL project which will control some LEDs of the Xilinx ZC702 board using switches.
Add the Board File to Vivado
If you are using a Xilinx ZC702 board or a Digilent ZedBoard, you shouldn’t need to do this step (the board should appear in the Boards List when selecting the default part).
If you are using a ZYBO, a zedboard, a basys3 or a nexys4, download the Board File from the digilent website (here). Unzip the folder and copy the folder: <zip_exracted_location>\vivado-boards-master\new\board_files\<board_name> in C:\Xilinx\Vivado\<version>\data\boards\boards_files.
Create a new project
Open Vivado and create a new RTL project. In the “Default Part” window, select the “ZYNQ-7 ZC702 Evaluation Board” (or the board you are using if other)
Figure 1 - Board choice in the “Default Part” window
Create the VHDL file
Create a new VHDL file (top_level.vhd). In the “Define Module” window, add to inputs (SW1_inp, SW2_inp) and two outputs (LED1_outp, LED2_outp).
Figure 2 - “Define Module” window
Open the VHDL file in the Vivado text editor and simply write the VHDL code to connect the SW1_inp to LED1_outp and SW2_inp to LED2_outp as shown in the Figure 3.
Figure 3 - Connect the signals
Then click on “Run Synthesis” in the “Flow Navigator”.
Create the physical constraints
We will have to tell Vivado which pin of the device corresponds to which input/output. For the two input signals, we will use the two little switches from the switch SW12 of the Xilinx ZC702 (or the switches SW0 and SW1 on the ZedBoard/ZYBO).
Figure 4 - GPIO DIP Switches (source: Xilinx UG850)
In the Figure 4 (from the Xilinx UG850) we can see that the two switches are connected to the pins W6 and W7 of the Zynq device on the board (from the ZYBO reference manual (https://reference.digilentinc.com/reference/programmable-logic/zybo/reference-manual), SW0 and SW1 are connected to G15 and P15 and from the ZedBoard User Guide (http://zedboard.org/sites/default/files/documentations/ZedBoard_HW_UG_v2_2.pdf), SW0 and SW1 are connected to F22 and G22).
Figure 5 - SW12, DS19 and DS20 on the Xilinx ZC702 board
For the two inputs, we will use the user LEDs DS19 and DS20 (LD0 and LD1 for the ZYBO/ZedBoard). In the Figure 5 (from the Xilinx UG850) we can see that the two LEDs are connected to the pins E15 and D15 of the Zynq device on the board (M14 and M15 for the ZYBO, T22 and T21 for the ZedBoard).
Figure 6 - User LED Connections (source: Xilinx UG850)
When the synthesis is finished click on “Open the synthesized design” on the “Synthesis completed” window (can also be opened from the Flow Navigator). You should have the “package” windows opened as shown in the Figure 7. If not, make sure the layout is “I/O planning” (also shown in the Figure 7) or click on “layout > I/O planning” from the menu.
Figure 7 - Package window
Create a new constraints file by clicking on “Add Sources” in the “Flow Navigator” and the selecting “Add Or Create constraints” in the “Add Sources” window. Name the file phys_const.
Figure 8 - Create constraints file
In the “I/O Ports” window, in the Package Pin columns enter E15 (M14 for ZYBO, T22 for ZedBoard) for LED1_outp, D15 (M15 for ZYBO, T21 for ZedBoard) for LED2_outp, W6 (G15 for ZYBO, F22 for ZedBoard) for SW1_inp and W7 (P15 for ZYBO, G22 for ZedBoard) for SW2_inp.
Figure 9 - I/O ports constraints
Enter LVCMOS25 in the column “I/O Std” for all the lines (LVCMOS33 for LED1_outp and LED2_outp on the Zedboard). Press Ctrl+S to save the constraints. If an “Out of Date Design” window appears, just click OK. Then a “Save Constraints” window should appear. Select “Select an existing file” and the constraints file we have created and click OK.
Figure 10 - “Save Constraints” window
If we open the file phys_const.xdc (from the Sources window), we can see that Vivado has saved in this file the constraints we have entered in the I/O ports window.
Figure 11 - File phys_const.xdc
Generate the Bitstream and program the FPGA
Click on “Run Implementation” in the “Flow Navigator”. When the implementation is completed, click on “Generate Bitstream”.
Figure 12 - Implementation Completed
When the Bitstream Generation is completed, click on “Open Hardware Manager”.
Figure 13 - Bitstream Generation Completed
Power on the board and make sure the board is connected to the PC (and you are not using a Virtual Machine). Click on “Open Target > Open New Target…”. Choose Local Server in the “Hardware Server Setting”.
Figure 14 - Open New Target
The tool should find your device as shown in the Figure 15.
Figure 15 - Open New Hardware Target
Then click on “Program Device” to program the FPGA.
Test on the board
On the board you should have two LEDs INIT and DONE. This two LEDs will indicate you if the configuration of the FPGA went well. If the INIT led is red, FPGA initialization is in progress and if it is green, FPGA initialization was successful. The DONE LED should be green if the FPGA have been configured successfully.
Figure 16 - INIT and DONE status LEDs
If the FPGA has been successfully programmed, the LEDs DS19 and DS20 value should change when we change the value of the switches of SW12.
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