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Analysing an HW design using an Integrated Logic Analyser (ILA)

Posted by Florent - 06 July 2017

Introduction

In this tutorial, we will add an Integrated Logic Analyser (ILA) in a block design to understand the communication on the AXI bus between the PS and the PL.

Create the Project

Follow the tutorial 9 to create a project using the AXI GPIO IP.

Mark the signals to Debug

In this tutorial we will analyse the communications between the PS and the PL by analysing the AXI interface between the AXI interconnect and the AXI GPIO IP.

Open the Block Design. Right Click on the bus from AXI Interconnect M00_AXI to AXI GPIO S_AXI and click “Mark Debug”.

Figure 1 - Mark the signals to Debug

Validate the Block Design. There should be no errors. Regenerate the output products and synthesize the design.

Add the Integrated Logic Analyser (ILA)

Open the synthesized design. The “Debug” window should open as you open the synthesized design. You can open this window manually by selecting “Window > Debug”. Then click on the “Set Up Debug” icon  on the left on the “Debug” window.

Figure 2 - Set Up Debug

In the “Set Up Debug” window, in the “Net to Debug” page, click on the “Filter” icon to display all the signal without an assigned clock domain. Select all the remaining signals, right click on the selection and click on “Select Clock Domain…”.

Figure 3 - ILA - Select Clock Domain

In the “Select Clock Domain” window, make sure that “FCLK_CLK0” is selected and click OK.

Figure 4 - Select Clock Domain

All signals captured by a single ILA core must have the same clock domain selection.

Click next > Next > Finish. Save the synthesized design, implement the design and open the implemented design.

Figure 5 - ILA in the implemented design Netlist

If the ILA has been correctly implemented, you should see it in the implemented Netlist.

Close the implemented design and generate the Bitstream.

Export the Hardware to SDK including the Bitstream and launch SDK.

Create the application project and launch the debug in Xilinx SDK

In SDK, you should have the application project from tutorial 9. Program the FPGA. Launch the GBD debug application (GDB).

Figure 6 - Show line number or add a Breakpoint in Xilinx SDK

Add a breakpoint on the line 40 (“if(direction == DIR_LEDS_RIGHT){“). If you want to show the line number in SDK, right click on the blue column on the left and click “Show Line Numbers”. To add a break point you can double click on the blue column in the correct line or right click and click “Add Breakpoint” and enter the correct line.

Go back to Vivado. Click on “Open Hardware Manager” in the “Flow Navigator”. Open the target. You should see the ILA window.

Figure 7 - ILA window in Vivado

In the small “Trigger Setup” window, click on the “+” icon and search for “AWVALID”. Select the signal.

Figure 8 - Set the signal AWVALID as probe

Change the compare value for “X” to “1”.

Figure 9 - Change the compare value of the probe signal

Change the value for “Trigger position in window” to “512”.

Figure 10 - Trigger position in window value

Launch the trigger for the ILA core by pressing the icon.

The statut of the ILA should change to “Waiting for Trigger”.

Figure 11 - ILA Waiting for Trigger

Resume the application in SDK (press F8). The program will stop at the breakpoint line. In Vivado, the ILA status should still be “Waiting for Trigger” as the software hasn’t changed the value of the LEDs. Resume again the debug application in SDK. In Vivado, the status of the ILA should have changed to “Idle” and the ILA should have captured the data.

Figure 12 - ILA capture of the signals

Analysing the data on the AXI interface

The Figure 13 shows the communication flow on the AXI interface to execute a write.

Figure 13 - Channel Architecture of Writes (Source Xilinx UG1037)

If we look at the AXI interface of the AXI GPIO IP on the Figure 14 we can see 5 groups of signal (identified by their name):

·        s_axi_aw*: signals corresponding to the write address channel

·        s_axi_ar*: signals corresponding to the read address channel

·        s_axi_r*: signals corresponding to the read data channel

·        s_axi_w*: signals corresponding to the write data channel

·        s_axi_b*: signals corresponding to the write response channel

Figure 14 - AXI GPIO IP

In our case we are executing a write using the AXI interface. As shown in the Figure 13, in the first step of the AXI write the master sends address and control data through the write address channel. In our waveform this corresponds to:

·        the address 0x41200000 is written by the master on *_AXI_AWADDR

·        the signal *AXI_AWVALID is set to 1 by the master to indicate this is a valid write request

In the second step, the master send the data to write:

·        data written on *_AXI_WDATA

·        signal *_AXI_WVALID is set to 1 by the master to indicate that the data written is valid

·        signal *_AXI_WREADY is set to 1 by the slave to indicate he is ready for a next data (if available)

In the last step, the slave indicates that the write operation is successful:

·        the signal *_AXI_BRESP is set to 1 by the slave

 

 



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